Convolution Accelerator

This project represents my final bachelor’s thesis, focusing on the comprehensive analysis of convolution functionality, from its software implementation to its hardware description as an accelerator. The accelerator is designed in two versions: one with a single multiplier for scenarios where area constraints are critical, and another with multiple multipliers to achieve faster computations. These multipliers are simplified versions with alternative designs to enhance performance, albeit with a slight reduction in accuracy. Ultimately, the convolution software code was executed on a multi-cycle RISC-V processor named AFTAB. The timing results were then compared to those obtained when the accelerator performed the same task using a custom instruction in AFTAB by taking advantage of my accelerator. This comparison highlighted the efficiency and performance gains achieved through hardware acceleration.

The codes are available here.