Documents                                                     

Resume [PDF] Updated March 19th. 2025

                     TOEFL Score Report [PDF] Updated July 24th. 2024

Interests                                                     

I have a keen interest in digital hardware design. I find it fascinating to integrate logic design with other areas such as brain computer interface applications, computer architecture, signal processing, and machine learning. I also believe that strong engineering skills are crucial for conducting high-quality research, so I constantly seek new experiences and strive to learn new things.

Recent News

I am accepted into the prestigious E3 Internship Program at EPFL. I will be working in the INL lab under the supervision of Professor Mahsa Shoaran. This exciting opportunity marks a significant milestone in my research journey.

Experiences: Skills and Learnings

Computer Aided Digital Design     

CAD Lab   2020 - Present

I specialize in digital logic design, covering steps from electronics system-level design to layout design and GDS file generation. My work spans ESL design, processors, accelerators, SoC frameworks, EDA tools, and Layout Design. Additionally, I have some experiences in CMOS design and have explored advanced Operational Transconductance Amplifier (OTA), Sample and Hold circuits, and ADCs in CMOS graduate course. My primary interests in logic design include hardware for machine learning, hardware for Deep Neural Networks (DNNs), AI hardware, and design implementations. For my graduate thesis, I am developing a BCI-based accelerator, creating a flexible architecture for hardware implementation of deep neural networks. Currently, I am focusing on EEG-Net architecture and motor imagery applications, exploring methods for area and power optimization, in order to make it suitable for chip implants.

These are some of my skills regarding programming and pertinent tools:

• C/C++

• Verilog/SystemVerilog/VHDL

• SystemC/SystemC-AMS

• ModelSim/QuestaSim

• Quartus/Vivado

• Cadence: Innovus - Virtuoso

• Synopsys: Design Compiler - Hspice/Hspice-MOSRA

• Calibre

• Yosys

• Chipyard

• Python: pytorch/tensorflow/keras

• EEG signals feature extraction and classification

• BCI (Brain Computer Interface)

     I have also become familiar with some other concepts throughout my courses:

    Undergraduate:

• Core-based Embedded Systems Design (GEM5, ASIP and openasip, VLIW, OOO Processors, Vector Processors, CUDA Programming)

• Digital Electronic Circuits (FET, Static CMOS, Logic Family, Adders, Sequential Logic Circuit, Fabrication, Stick Diagrams, Design Rules, Packaging)

• Electronic System Level Design (HLS, CatapultC, MATLAB HDL Coder, CHISEL)

• FPGA-based Embedded Systems Design (ALTERA FPGAs, Qsys, Nios II SBT for eclipse, Timing Analysis)

• Introduction to Digital System Design Algorithms (Software Algorithms, Data Structure, Design Cycle, Optimization)

• Object Oriented Modeling of Electronic Circuits (C++, SystemC, SystemC-AMS)

• Parallel Programming (SIMD, OpenMP, POSIX, Intel Parallel Studio, CUDA)

  Graduate:

• Advanced Computer Architecture (Pipeline, Memory Hierarchy, Superscalar, VLIW, Advanced Cache, Branch Prediction, Address Translation and Protection, Vector Processor, GPU, SIMD, Multithreading)

• Advanced VLSI (MOS Device, Interconnects, Combinational Logic, Sequential Logic, Implementation Methodologies, FPGAs, Designing Arithmetic Building Blocks, Semiconductor Memories, Manufacturing Process, Packaging)

• Computer Arithmetic (Conventional and Unconventional Numbering Systems, Adders, Signed Digit Adder, Multi Operand Addition Architecture, Multiplication Architecture, Division Architecture, Floating Points Architecture)

• Neural Network (Autoencoders, CNNs, RCNN, RNN, Transformers, GANs)

• CMOS (Operational Transconductance Amplifier (OTA), Sample and Hold circuits, and ADCs)

• Low-Power Design (Methods for power reduction in digital circuits)

• Verification (Formal Verification)

• VHDL (VHDL, SystemC, SystemC-TLM)

Internship                           

Crouse PJS Co. [Website]  2021

I embarked on this internship with the goal of deepening my understanding of digital design. During my time here, I had the opportunity to develop an Instruction Set Simulator (ISS) for the RL78 processor using SystemC. This task was a crucial component of an advanced project aimed at creating a comprehensive virtual platform. Through this experience, I was able to apply my theoretical knowledge in a practical setting, significantly enhancing my skills in digital design and simulation.

These are some of my skills regarding this program:

• Open Virtual Platform

• SystemC

• C++

• RL78 instructions, memory map, and registers

Current Projects

I am working on some projects, which are as follows:

• Studying and exercising open-source tools for VLSI flow and SoC frameworks.

• Design of a SoC with cryptographic modules.

• Thesis project: Design of a flexible hardware for deep neural networks for BCI applications.  

Publications

HIRMA: High-Performance Implementation for RISC-V Microcontroller Applications

2023 IEEE East-West Design & Test Symposium (EWDTS) 2023

This paper presents a comprehensive flow from design to implementation of a fully synthesizable 32-bit microcontroller in 180nm CMOS technology. Named HIRMA, this microcontroller incorporates the open-source RISC-V IM processor, connected via customized buses for communication. It includes a 4kB SRAM, an SPI flash controller for loading instructions from external flash to SRAM, a UART module for transmission and reception, a 32-bit timer, and support for external off-chip accelerators. All peripherals are managed by the RISC-V processor, with an SPI master interface used for programming the SRAM. The paper details the design of the microcontroller and outlines the design flow from Register-Transfer Level (RTL) to layout generation. Additionally, it introduces an affordable and easy-to-implement platform for post-manufacturing testing. The microcontroller has a total power density of 10.7091mW at 50 MHz and occupies a compact area of 1mm × 2mm, including I/O pad modules.

An Integrated Framework for Creating System-Level Compatible Age-Aware Library Cells 

Admitted for IEEE ETS 2025

Designers are often compelled to make compromises to ensure reliable functionality as transistors age, which can hinder efficiency. Conventional aging analysis tools are slow and impractical for complex circuits. Thus, this study introduces a gate-level back-annotation of aging characteristics that improves simulation efficiency and retains accuracy at an acceptable level. This method is used in a uniform framework that brings in aging considerations in an event-based simulation environment and automates the extraction of the required information to fit in the mentioned environment. This results in the calibration of simulation units defined as gate models for bridging device-level to system-level analysis. Considering today’s digital design complexities, this work incorporates the conventional aging analysis into an event-based simulator, which provides much faster analysis time. This approach achieves an average speedup of 7.12 versus HSPICE and maintains accuracy with an average pessimism of 0.29%, making it a practical environment for analyzing aging effects on reliability. 

             Some of my projects are explained here.