Instruction Set Simulator of RL78

In this project, I developed an instruction set simulator (ISS) for a processor called RL78 using SystemC. This simulator provides a cycle-accurate representation of the processor at the system level. While it doesn’t delve into the specifics of signaling, it allows us to obtain the overall results of running applications much more quickly than traditional RTL (Register Transfer Level) simulations. The implementation methodology is highly adaptable, making it suitable for creating ISS for other processors as well. This approach is particularly beneficial for virtual platforms that require abstract-level program results delivered as swiftly as possible.

The codes are available here.

The following pictures describe a conventional methodology for ISS.

The following pictures describe the new methodology for ISS, which is based on Open Virtual Platform (OVP) instruction set simulators.